1. Technical Field of the Invention
This invention relates to memory circuits, and more particularly to SRAM memory circuits.
2. Description of Related Art
As a result of the never-ending quest to integrate more circuitry onto a single integrated circuit, designers are driven to find ways in which to increase the density of their circuit designs. The goal of integrating entire systems on a chip (SOC) has resulted in the motivation to include more memory capacity for those systems, particularly in view of the speed advantage in accessing integrated memory rather than off-chip.
One of the ways in which circuitry in general has become more dense is to simply shrink the circuitry photolithographically. Although steady gains in the ability to further shrink feature sizes has been beneficial, the rate at which such gains are being made has tapered off recently. Another technique for making circuits smaller is to eliminate devices from the circuit design. This can reduce not only the silicon real estate occupied by the circuit devices, but also the additional interconnect typically required for those devices.
With respect to memory cells, and SRAM cells particularly, attempts have been made to reduce their gate count while maintaining proper performance and reliability. FIG. 1 illustrates a standard prior art SRAM cell. Access transistors 30 and 14 isolate the cell and selectively access the cell during read and write operations. Transistors 9 and 7 are storage transistors that effectively store a binary one and zero state on the Q 28 and Qbar 18 output nodes of the cell. The storage transistors can be pull-up or pull-down transistors, depending upon the design of the cell. In the case of the cell in FIG. 1, they are pull-down transistors. The state of the cell is programmed during a write operation, and then isolated by the access transistors. The bi-stable nature of the storage devices is designed to hold the state until it is flipped by a write of an opposite polarity.
The P-channel transistors 24, 20 perform two functions in the cell of FIG. 1. First, they can assist a change of state to VDD during a write operation that is flipping the state of the cell. The second function is to supply charge to nodes 28 and 18 during the idle state. By doing so, they effectively replenish charge lost from isolated nodes 28 and 18 (whichever is at VDD) due to leakage through the pull-down storage transistors 9, 7. Although access transistors can and do provide some replenishing charge to nodes 28 and 18 (whichever is at VDD) through leakage current of their own, the magnitude of the leakage they provide by itself is not guaranteed to be sufficient to exceed the outflow from output nodes 28, 18, which is required to maintain the VDD state.
One way to shrink a cell such as the one in FIG. 1 is to replace the p-channel pull-ups 24, 20 with resistors. This can provide some additional density if the resistors can be implemented on a separate integrated circuit processing layer such that the resistors can overlap the cell transistors. Another solution is to simply eliminate the pull-up transistors altogether. The assistance they provide in flipping the cell state is not absolutely necessary, and in fact while one is helping, the other is actually resisting the change in state on the other side of the cell, increasing the power dissipation and write time of the cell. It is because the pull-ups are always the weakest of the three types of devices that the cell operates correctly. However, if the pull-up transistors are eliminated, there must be another way to ensure that the leakage provided by the access transistors is not exceeded by the leakage out of the nodes 28, 18, or the VDD state on one of the output nodes will deteriorate over time. This is difficult because the proper operation of the cell requires that the storage device be the largest and therefore the strongest in terms of current.
As a result, eliminating the p-channel devices as a solution to shrinking the memory cell has met with varying success. Some additional important points with regard to the operation of the SRAM cell of FIG. 1 should be noted. There is a hierarchy with respect to the relative strength of the devices in the SRAM cell. Storage transistors 9 and 7 should be the strongest transistors. Slightly less strong are the access transistors 30, 14. The weakest transistor will be the P-channel pull-up transistors 24, 20. The reason that the storage transistors 9, 7 must be stronger than the access transistors 30, 14 is that during a read operation, the access transistor 30, 14 should not be so strong as to disturb the state of the SRAM cell during the read. This is referred to as the beta ratio which is the ratio of relative strength between the pull-down transistors 9, 7 and the access transistors 30, 14. Typically, a beta ratio of greater than 1.5 is desirable to ensure that the cell is stable and will not be disturbed during a read access. This ratio virtually assures that the leakage supplied by the access transistor will not exceed the leakage through the storage devices.
Therefore, there is still a need in the art for SRAM cells that are as device efficient as possible, while still providing optimal and reliable performance.
An embodiment of a dense memory cell in accordance with the invention includes two access transistors, each having a gate tied to a wordline input, a first one of the access transistors having a drain and source coupled between a bit line and an output node. The cell further includes two storage transistors, a first one having a drain and source coupled between the output line and a power signal and a gate couple to an output bar node, the second one having a drain and source coupled between the output bar node and the power rail, and a gate coupled to the output node. The cell also has a control circuit generating a tracking voltage coupled to the wordline, the track voltage for adjusting the voltage on the wordline during an idle state to ensure that leakage current through the two access transistors exceeds the leakage through the two storage transistors where the output node to which it is coupled is at VDD. The track voltage is a function of a reference voltage determined to provide a leakage through the access transistors that exceeds the leakage through the storage devices. The tracking voltage is buffered to substantially reduce disturbances to a reference voltage resulting from switching states on the wordline.
An embodiment of tracking circuit that generates the tracking voltage is a reference circuit, the reference circuit that includes a plurality of partial memory cells, each partial memory cell comprising one access transistor and storage transistor configured in a worst case leakage condition. It includes a differential amplifier having a voltage reference input and a second input coupled to an output node of each of the partial memory cells, the output of the differential amplifier being the tracking voltage.
An embodiment of the memory cell of the invention includes two access transistors, each having a gate tied to a well bias input, a first one of the access transistors having a drain and source coupled between a bit line and an output node, and two storage transistors, a first one having a drain and source coupled between the output line and a power signal and a gate couple to an output bar node, the second one having a drain and source coupled between the output bar node and the power signal, and a gate coupled to the output node. A control circuit generating a tracking voltage is coupled to the well bias. The track voltage for adjusting the voltage on the well bias during an idle state ensures that leakage current through the two access transistors exceeds the leakage through the two storage transistors where the output node to which it is coupled is at VDD.
An embodiment of the memory cell of the invention includes two access transistors, each having a gate tied to a power signal input, a first one of the access transistors having a drain and source coupled between a bit line and an output node. It further includes two storage transistors, a first one having a drain and source coupled between the output line and the power signal and a gate couple to an output bar node, the second one having a drain and source coupled between the output bar node and the power rail, and a gate coupled to the output node. It further includes a control circuit generating a tracking voltage coupled to the power signal, the track voltage for adjusting the voltage on the power signal during an idle state to ensure that leakage current through the two access transistors exceeds the leakage through the two storage transistors where the output node to which it is coupled is at VDD.